Introduction
The global semiconductor industry is evolving at an unprecedented pace, and advanced packaging technologies have become pivotal in enhancing chip performance and market competitiveness. As we gradually approach the physical limits of Moore’s Law, simply relying on shrinking process nodes to boost performance and reduce costs is no longer economically viable. Consequently, major wafer foundries and assembly/testing companies are actively investing in heterogeneous integration and advanced packaging techniques to improve chip interconnect efficiency, lower power consumption, and bolster system integration capabilities for Artificial Intelligence (AI), High Performance Computing (HPC), 5G communications, and autonomous vehicles applications.
Taiwan is highly competitive in the field of advanced packaging due to its comprehensive semiconductor supply chain. Industry leaders including TSMC, UMC, ASE, and SPIL are proactively adopting next-generation packaging technologies such as Fan-Out Packaging (FOP), 2.5D/3D ICs, heterogeneous integration System-in-Package (SiP), and Co-Packaged Optics (CPO). These innovations significantly enhance chip performance and power efficiency, as well as further consolidate Taiwan’s leadership in the global semiconductor packaging market.
Global Advanced Packaging Technology Development
Traditional packaging technologies primarily adopt horizon approaches, whereas advanced packaging technologies enhance chip performance and reduce power consumption by stacking multiple chips either horizontally or vertically—much like building blocks—to integrate chips of various process nodes. The development of advanced packaging is moving toward multi-dimensional integration, where heterogeneous integration is becoming increasingly prevalent. By stacking chips with different functionalities (e.g., logics and memory) within a single package, advanced packaging significantly boosts computing performance and lowers power consumption, making it a critical technology for High Performance Computing (HPC) and Artificial Intelligence (AI) chip design. Going forward, advanced packaging will evolve toward higher integration density, shorter signal transmission distances, and reduced power consumption. Major global advanced packaging technologies include:
- Fan-Out Packaging (FOP)
This technology achieves higher I/O (input/output) density—where I/O refers to data transmission channels between the chip and external devices—by increasing both the number and density of I/Os. In doing so, FOP improves signal transmission efficiency, reduces latency, and significantly decreases system size. It also eliminates the need for traditional substrates and reduces overall package volume. As a result, Fan-Out Packaging is widely adopted in 5G, HPC, and AI chips.
- 2.5D/3D IC Packaging
In 2.5D packaging, chips are partially stacked, whereas 3D packaging involves fully stacking multiple chips. Using Through-Silicon Vias (TSVs) and chip stacking techniques—along with an interposer—enables vertical integration of different functional chips, thereby enhancing computing performance and signal transmission efficiency while lowering power consumption.
- Heterogeneous Integration and High-Density Packaging
Global leader in semiconductor packaging and testing, Amkor, has been actively investing in heterogeneous integration and high-density advanced packaging technologies. Focus includes High-Density Fan-Out (HDFO) and System-in-Package (SiP) solutions, as well as bolstering High Bandwidth Memory (HBM) packaging integration. By collaborating with leading memory and Graphics Processing Unit (GPU) suppliers worldwide, Amkor is driving advancements in AI and HPC chips.
- Co-Packaged Optics (CPO)
CPO integrates optical components and electronic chips (e.g., processors or switch chips) within the same chip or module. This approach shortens the optical path, reduces power consumption, and increases data transmission rates.
Taiwan’s Focus on Advanced Packaging and Testing
Taiwan occupies a pivotal position in the global semiconductor industry, especially in the realm of advanced packaging. With rising demand for AI and HPC, advanced packaging has become pivotal to industry growth. The following are several key areas of development for Taiwan in advanced packaging:
- 2.5D/3D IC with Chip-on-Wafer-on-Substrate (CoWoS) is in high demand and short supply
Leveraging CoWoS, TSMC has expanded its business from pure wafer foundry services into packaging. By integrating multiple chips on an interposer within a single package, CoWoS enhances signal transmission and reduces power consumption. CoWoS is divided into two parts—“CoW” (Chip-on-Wafer), referring to chip stacking, which offers higher technical complexity and profit margins, and “WoS” (Wafer-on-Substrate), which stacks the chip onto a substrate. Depending on the layer arrangement, there are 2.5D and 3D formats, currently applied mainly to HBM and AI computing chip integration.
- Fan-Out Panel Level Packaging (FOPLP)
FOPLP uses a glass substrate instead of the traditional circular wafer, increasing production capacity and lowering costs. There are two approaches for companies entering the FOPLP market: one involves panel manufacturers expanding into semiconductor packaging technologies (e.g., Innolux), and the other involves foundries (wafer fabrication) and OSAT (assembly/testing) providers shifting from wafer-level to panel-level packaging (e.g., TSMC, ASE, Powertech). Currently, FOPLP is primarily used for mature processes, such as those in automotive and IoT applications.
- Heterogeneous Integration and Hybrid Bonding Packaging
UMC has actively pursued advanced packaging, focusing on wafer-on-wafer hybrid bonding and package-on-package (PoP) technologies to increase chip interconnect density, shorten signal transmission distances, and improve packaging efficiency. In addition, UMC is enhancing HBM packaging and advancing heterogeneous integration System-in-Package (SiP) to strengthen HPC and AI capabilities.
- Future Key Developments in Advanced Packaging
The technology that integrates optoelectronic modules with chip packaging, known as Co-Packaged Optics (CPO), is emerging as a critical development. With the surge of generative AI, cloud service providers requiring vast computational resources are facing explosive data growth, making the construction of data centers a major driving force behind CPO. The commercialization of CPO is expected to be a key focus moving forward.
Conclusion
Taiwan’s advanced packaging industry has become a major pillar of the global semiconductor sector. With proactive investments from TSMC and other key players, Taiwan is set to further consolidate its global leadership. Looking forward, 2.5D/3D IC, chiplet packaging, and CoWoS technologies will drive growth in the packaging and testing market, while boosting an upgrade in material demand. Taiwan’s competitive advantages in packaging include:
- A Comprehensive Semiconductor Value Chain
Including IC design, wafer manufacturing, and assembly/testing, offering robust integration capabilities.
- TSMC’s Technological Leadership
Featuring the world’s most advanced 2.5D/3D IC packaging technologies, which attract global collaboration.
- Government Policy Support
Providing land, talent, and tax incentives to foster industrial cluster development.
Overall, Taiwan’s packaging industry is poised for continued expansion and will remain a critical force in the global semiconductor market.
Source： Analysis Team, Commercialization and Industry Service Center, Industrial Technology Research Institute (ITRI)
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